1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor storage device. More particularly, it relates to the configurations of a contact plug and a wiring line in a NAND type flash memory.
2. Description of the Related Art
There has been remarkable advancement in the recent miniaturization of semiconductor devices. Along with this miniaturization, the wiring width and wiring pitch of a metal wiring layer have been reduced.
A conventional metal wiring layer is formed by, for example, embedding a conducting layer in a groove formed in an interlayer insulating film. In this regard, there is widely used a method of previously forming, in the interlayer insulating film, an insulating film which functions as an etching stopper during the formation of the groove (see, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2005-116970 or Jpn. Pat. Appln. KOKAI Publication No. 2003-045964 or Jpn. Pat. Appln. KOKAI Publication No. 07-335757).
However, the dielectric constant of a material used for the insulating film which functions as the etching stopper is generally higher than that of a material used for the interlayer insulating film. Therefore, if this insulating film is present in the metal wiring layer, the parasitic capacitance between the metal wiring layers increases.
Particularly in the case of a semiconductor memory requiring higher integration, for example, an electrically erasable and programmable read only memory (EEPROM), adjacent bit lines are formed with minimum processing dimensions. This has caused the problem of decreased operation reliability of the semiconductor memory, such as a decreased operation speed, when the parasitic capacitance increases.